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= What does "deferred" actually mean in various GPUs? = | = What does "deferred" actually mean in various GPUs? = | ||
The best document that I could find on this is [http://www.imgtec.com/powervr/insider/docs/POWERVR%20Series5%20Graphics.SGX%20architecture%20guide%20for%20developers.1.0.8.External.pdf POWERVR Series5 Graphics], section 3. However, we won't use exactly the terminology of this document because it reserves the word "deferred" solely for PowerVR's version of "deferred". | |||
In our terminology here, are 3 types of GPUs: immediate, tile-based deferred rasterization, and tile-based deferred HSR, where '''HSR stands for Hidden Surface Removal'''. | |||
We will abbreviate "tile-based deferred rasterization" as '''tbd-rast''' and "Tile-based deferred HSR" as '''tbd-hsr'''. | |||
Here's a table summarizing how this maps to various GPU vendors' terminology, what GPUs fall into which category, and what each term actually means. | |||
{|class="wikitable" | |||
!rowspan="2"|Our terminology | |||
|rowspan="2"|Immediate | |||
|colspan="2" style="text-align: center" |Deferred | |||
|- | |||
|Tile-based deferred rasterization, abbreviated as '''tbd-rast''' | |||
|Tile-based deferred HSR, abbreviated as '''tbd-hsr''' | |||
|- | |||
![http://www.imgtec.com/powervr/insider/docs/POWERVR%20Series5%20Graphics.SGX%20architecture%20guide%20for%20developers.1.0.8.External.pdf ImgTec terminology] | |||
|Immediate rendering | |||
|Tile-based rendering (TBR) | |||
|Tile-based deferred rendering (TBDR) | |||
|- | |||
![http://infocenter.arm.com/help/topic/com.arm.doc.dui0555a/DUI0555A_mali_optimization_guide.pdf ARM terminology] | |||
|Immediate rendering | |||
| scope="row" colspan="2" style="text-align: center" |Interchangeably "tile-based rendering" or "tile-based deferred rendering" | |||
|- | |||
!Hardware | |||
|NVIDIA Tegra, desktops | |||
|ARM Mali, Qualcomm Adreno | |||
|ImgTec PowerVR | |||
|- | |||
!Meaning | |||
|Submitted geometry is immediately rendered; no tiling is used. | |||
|Submitted geometry is immediately transformed and stored in per-tile lists. Rasterization is then done separately for each tile. | |||
|Submitted geometry is immediately transformed and stored in per-tile lists. HSR is then done for each tile, yielding a list of visible fragments. | |||
|- | |||
|Performance implications | |||
|Good old desktop GPU optimization | |||
|Optimizations discussed below for deferred GPUs | |||
|Optimizations discussed below for deferred GPUs, plus there is no need for front-to-back sorting, as HSR is efficiently handled by hardware. | |||
|} | |||
= Performance implications of "deferred" = | = Performance implications of "deferred" = | ||